Efficient Time-to-Digital Converters in 20 nm FPGAs With Wave Union Methods

Time-interleaved Analog-to-digital Converters for Digital Communications

Techniques to overcome the errors caused by the offset, gain, and sample-time mismatches among timeinterleaved analog-to-digital converters (ADCs) in highspeed digital communication systems are presented. The errors introduced by these mismatches are adaptively corrected using digital signal processing blocks. Sampletime errors are corrected by modifying the operation of the existing adaptive r...

Run-time power and performance scaling in 28 nm FPGAs

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Achieving One TeraFLOPS with 28-nm FPGAs

Due to recent technological developments, high-performance floating-point signal processing can, for the first time, be easily achieved using FPGAs. To date, virtually all FPGA-based signal processing has been implemented using fixed-point operations. This white paper describes how floating-point technology on FPGAs is not only practical now, but that processing rates of one trillion floating-p...

Digitally Enhanced Continuous- Time Sigma-Delta Analogue-to-Digital Converters

Compact, Low-Cost Direction-Finding Using Time to Digital Converters

Previous work within an EMRS DTC funded project focussed on investigating a method of implementing TDOA for low-cost UAV or land vehicle applications, using a Commercial Off The Shelf (COTS) Time-to-Digital Converter (TDC). The technology demonstrator was designed and constructed, adopting a short baseline of only 2m, and tested briefly on commercial emitters. This year’s project work was based...